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MIPS R4000 User's Manual Second Edition

This book describes the MIPS R4000 and R4400 family of RISC microprocessors (also referred to in this book as processor).

Overview of the Contents

• Chapter 1 is a discussion (including the historical context) of RISC development in general, and the R4000 microprocessor in particular.
• Chapter 2 is an overview of the CPU instruction set.
• Chapter 3 describes the operation of the R4000 instruction execution pipeline, including the basic operation of the pipeline and interruptions that are caused by interlocks and exceptions.
• Chapter 4 describes the memory management system including address mapping and address spaces, virtual memory, the translation lookaside buffer (TLB), and the System Control Processor (CP0).
• Chapter 5 describes the exception processing resources of R4000 processor. It includes an overview of the CPU exception handling process and describes the format and use of each CPU exception handling register.
• Chapter 6 describes the Floating-Point Unit (FPU), a coprocessor for the CPU that extends the CPU instruction set to perform floating-point arithmetic operations. This chapter lists the FPU registers and instructions.
• Chapter 7 describes the FPU exception processing.
• Chapter 8 describes the signals that pass between the R4000 processor and other components in a system. The signals discussed include the System interface, the Clock/Control interface, the Secondary Cache interface, the Interrupt interface, the Initialization interface, and the JTAG interface.
• Chapter 9 describes in more detail the Initialization interface, which includes the boot modes for the processor, as well as system resets.
• Chapter 10 describes the clocks used in the R4000 processor, as well as the processor status reporting mechanism.
• Chapter 11 discusses cache memory, including the operation of the primary and secondary caches, and cache coherency in a multiprocessor system.
• Chapter 12 describes the System interface, which allows the processor access to external resources such as memory and input/output (I/O). It also allows an external agent access to the internal resources of the processor, such as the secondary cache.
• Chapter 13 describes the Secondary Cache interface, including read and write cycle timing. This chapter also discusses the interface buses and signals.
• Chapter 14 describes the Joint Test Action Group (JTAG) interface. The JTAG boundary scan mechanism tests the interconnections between the R4000 processor, the printed circuit board to which it is mounted, and other components on the board.
• Chapter 15 describes the single nonmaskable processor interrupt, along with the six hardware and two software processor interrupts.
• Chapter 16 describes the error checking and correcting (ECC) mechanisms of the R4000 processor.

R4300i Datasheet

The R4300i is a low-cost RISC microprocessor optimized for demanding consumer applications. The R4300i provides performance equivalent to a high-end PC at a cost point to enable set-top terminals, games and portable consumer devices. The R4300i is compatible with the MIPS R4000 family of RISC microprocessors and will run all existing MIPS software. Unlike its predecessors designed for use in workstations, the R4300i is expected to lower the cost of systems in which it is used, a requirement for price-sensitive consumer products. The R4300i is also an effective embedded processor, supported by currently available development tools and providing very high performance at a low price-point.

Overview

The success of the MIPS R3000 processor and its derivatives has established the MIPS architecture as an attractive high-performance choice in emerging consumer applications such as interactive TV and games. The R4300i is the 64-bit successor to the R3000 for this class of applications. It is specifically designed to be extremely low-cost from the outset, yet supply the performance necessary for full interactivity.

The R4300i achieves its low-cost goal by holding to a very small die size, simple package and low testing costs. It is further enabled for consumer applications by easily interfacing to other low-cost components. Its low power consumption also reduces system cost by combining high clock speed with limited power drawn, saving on power supply and heat dissipation costs.

The R4300i has a number of design features to reduce power. These include an all-dynamic design, unified integer and floating-point datapath, a reduced power mode of operation, and caches partitioned into separate banks.

Printers, networking devices and other embedded applications will also benefit from the high performance, low cost and high-bandwidth interface of the R4300i. The R4300i is the next standard in low-cost processing in the MIPS Microprocessor family.

MIPS IV Instruction Set

This appendix describes the instruction set architecture (ISA) for the central processing unit (CPU) in the MIPS IV architecture. The CPU architecture defines the non-privileged instructions that execute in user mode. It does not define privileged instructions providing processor control executed by the implementation-specific System Control Processor. Instructions for the floating- point unit are described in Appendix B.

The original MIPS I CPU ISA has been extended in a backward-compatible fashion three times. The ISA extensions are inclusive as the diagram illustrates; each new architecture level (or version) includes the former levels. The description of an architectural feature includes the architecture level in which the feature is (first) defined or extended. The feature is also available in all later (higher) levels of the architecture.

The practical result is that a processor implementing MIPS IV is also able to run MIPS I, MIPS II, or MIPS III binary programs without change. The CPU instruction set is first summarized by functional group then each instruction is described separately in alphabetical order. The appendix describes the organization of the individual instruction descriptions and the notation used in them (including FPU instructions). It concludes with the CPU instruction formats and opcode encoding tables.

N64 Annotated Circuit Board

Useful document that describe every chip of Nintendo 64 PCB.

N64 Joystick Port Pinout

Tired of those playstation people with their cheap homemade memory card interface, gonna roll my own in a very near future...

Pinout coming from a memory pack, pin names are in relation to a standard SRAM chip.

Nintendo 64 Controller FAQ

This work was done via reverse engineering the controller itself. No information was obtained via outside channels. All work was done on a N64 controller with no prior knowledge of its working. The hope was to interface the controller with a common pc game interface. Now working on full ISA interface.

N64 ToolKit : Opcodes

This is a collection of programming information for the Nintendo 64 that i've gathered. It is currently splitted into these parts:

• n64ops#a.txt - Brief list of R4300i opcodes
• n64ops#b.txt - Detailed list of R4300i opcodes
• n64ops#c.txt - R4300i opcode matrix
• n64ops#d.txt - Brief list of RSP opcodes
• n64ops#e.txt - Detailed list of RSP opcodes
• n64ops#f.txt - RSP opcode matrix
• n64ops#g.txt - ROM header information
• n64ops#h.txt - Nintendo 64 memory map

Contributed by other people:

• rcp.txt - RCP information, opcodes etc.
• sound.txt - How to play sound on the N64.
• controll.txt - How to access the N64 controller.

If you find any errors in the text, or miss anything, please inform me about that, either by email or ICQ #: 3299208.

N64 Memory Maps

n/a [ Read ]

by n/a

Nintendo 64 Memory maps, summary:

• ROM HEADER
• MEMORY MAP OVERVIEW
• MEMORY MAP DETAILED
• CONTROLLER
• SUOND
• INSTRUCTION

How to make a N64 trainer

n/a [ Read ]

by Icarus

Ladies and gentleman, Welcome to my "How to make a N64-Trainer" documentation.

The reason why i did this doc is very simple: i am quitting all my activities in the "n64-scene" for many reasons, i think you don't care for so i won't go into that any further. Furthermore it would be nice to see more groups doing trainers. So i hope this will help some dudes to start!

So however, let's come to the real documentation.

First i want to explain how my trainers are working.. I think you all know the hardware game-enhancers like "Action Replay", "Gameshark", "Gamebuster" and so on...

N64 Hardware Dox

v0.5 [ Read ]

by LaC

This little doc is my attempt to make the n64 coding scene a little better I hope. It is a compilation of stuff i've been working on for some months... a result of alot of reversing of several games compiled with libultra, and some help from certain people. It is mainly for people who wish to code without using a developement library (like libultra). It is specfically for doing intros,trainers, etc... to attach to roms. It is very simplistic, and assumes you have some knowledge already. In other words this doc isnt really meant for people just starting. You should probably have read the libultra docs and be familiar with the n64 hardware... and the purpose of things like the AI,PI,SI,VI etc...

I suppose some emulation author could find use of this too. Some people will probably be mad I released this doc, but I guess since nothing is really happening in the n64 scene it might get things moving? Especially from people that really want to hack. Also I have noticed some really crappy and inaccurate info being released which basically looks like stuff ripped from czn intros or something and contains no real knowledge. Yes all you freedom of information people... you want info... hack it yourself. Or read this doc, then hack some more ;)

Also I can't guarantee the 100% accuracy of any of this document. Also I liked to be greeted if you are using my dox or my source code in your work.